Turning to FIG. 1, illustrated is a conventional PLL 100. A resistor Rcp 155 is used in the PLL 100 for stability purposes, such that a “zero” is created in the loop transfer function, and ensures stability around the unity gain frequency. However, the total phase noise (jitter) of the PLL can be problematic.
Other approaches to solving various issues with PLL loops, such as phase noise characteristics, have been proposed, such as U.S. Pat. No. 6,420,917 B1 to Klemmer, entitled “PLL Loop Filter With Switched-Capacitor Resistor.” However, there seems 3 disadvantages with this architecture: 1.) There is a need of extra cap and it might increase the overall loop filter area by 15%, 2.) a non overlapping clock generator is needed to generate the control signals for the switched cap, 3.) two big switches are needed for the switched cap network (Q1 & Q2 in the FIG. 4 of Klemmer), which may add some switching noise at the ‘VCTRL’ node due to coupling through the parasitic capacitors.
Therefore, there is a need in the art to address at least some of the issues associated with conventional PLL circuits.